(1) Field of the Invention
The present invention relates to the fabrication of semiconductor structures, and more particularly, to a method to fabricate copper interconnects in the manufacture of integrated circuits.
(2) Description of the Prior Art
As integrated circuit feature sizes continue to decrease, it has become advantageous to construct metal connections out of copper instead of aluminum. Copper has a lower resistivity than aluminum, and therefore can form higher speed connections for a given line width.
The disadvantage of copper, however, is that it is more difficult to reliably etch than aluminum. To create copper traces, therefore, alternative design approaches such as damascene and dual damascene structures have been employed. By using damascene techniques, copper line etches are eliminated. Instead, trenches are first cut into the isolation dielectric material where connective traces are planned. Then the copper is deposited to fill the traces. A polishing process is then used to etch back any overfill of copper in the trenches. In this way, damascene approaches allow the use of copper for interconnects.
As practiced in the art, the copper interconnect processes that use damascene and dual damascene techniques experience several problems. Referring to FIG. 1, a cross-section of a partially completed prior art dual damascene structure is shown. A substrate layer 8 is depicted. The substrate layer 8 encompasses all underlying layers, devices, junctions, and other features that have been formed prior to the deposition and definition of the conductive plugs 12 in the isolation layer 10. A first intermetal dielectric layer 14 overlies the isolation layer 10 and partially overlies the conductive plug 12. An etch stopping layer 18 overlies the first intermetal dielectric layer 14. A second intermetal dielectric layer 22 overlies the etch stopping layer 18.
A via opening is shown formed in the first intermetal dielectric layer 14 to expose the top surface of the conductive plug 12. The via opening has a width L2. A metal interconnect opening is shown formed in the second intermetal dielectric layer 22. The metal interconnect opening has a depth of L3. The total depth of the dual damascene opening is L1.
Several problems can be illustrated regarding the prior art dual damascene structure shown in FIG. 1. First, the via opening is typically etched through both the first and second intermetal dielectrics, 14 and 22 respectively. This means that a large aspect ratio (L1/L2) etch must be made. It is difficult to make such etches uniformly in the production process. In addition, it is difficult to properly clean the etch opening after the etch process. Second, in the prior art structure, the etch stopping layer 18 must be used to control the depth of the metal interconnect trench. The etch stopping layer 18 is typically composed of silicon oxynitride. Unfortunately, silicon oxynitride has a relatively large dielectric constant when compared to the oxide material used in the dielectric layers. This means that the etch stopping layer 18 has the disadvantage of adding to the capacitance loading on the metal interconnect lines formed by this method.
The third disadvantage of the typical prior art dual damascene structure is the difficulty of filling the structure with the copper metal without creating gaps or voids. Even with the benefit of the stair step profile of the dual trenches, it is still difficult to properly fill the structure using physical vapor deposition (PVD) or chemical vapor deposition processes (CVD).
Referring now to FIG. 2, another approach to copper metalization is shown. Prior to the development of dual damascene techniques, the traditional metal deposit and etch technique was used to form metal interconnections with aluminum or aluminum alloys. In FIG. 2, a layer of copper metal 26 is shown deposited and etched to form connective features. The problem with using copper instead aluminum in this approach is the difficulty of etching copper deposited by PVD or CVD with reactive ion etching (RIE). Additionally, exposed copper surfaces 30 are very susceptible to corrosion during subsequent semiconductor processing. Etching difficulty and corrosion problems are the reasons dual damascene has become common in the art for copper metalization. However, dual damascene processing is complex and expensive. In addition, as seen in the earlier discussion, several problems exist in the dual damascene approach.
Several prior art approaches attempt to improve the viability of copper metalization. U.S. Pat. No. 5,731,245 to Joshi et al teaches the formation of copper-germanium alloys to improve the characteristics of soft metal and metal alloys. U.S. Pat. No. 5,420,069 to Joshi et al discloses a process to form a corrosion resistant layer of CuxGey overlying a copper conductor using a germanium gas source in a chemical vapor deposition chamber. U.S. Pat. No. 5,060,050 to Tsuneoka et al teaches a copper layer covered by an impurity diffusion-preventing layer. U.S. Pat. No. 4,931,410 to Tokunaga et al discloses a patterned copper interconnect process. U.S. Pat. No. 5,824,599 to Schacham-Diamond et al teaches an electroless copper deposition process to form copper interconnects. This process features a protective aluminum layer and uses chemical mechanical polishing to define the copper connections.
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating integrated circuits with copper interconnects.
A further object of the present invention is to provide a method of fabricating copper interconnects using electrochemical deposition of copper to improve the etching capability of the copper.
Another further object of the present invention is to provide a method of fabricating copper interconnects where a copper-germanium alloy passivation layer is formed over the exposed copper surfaces to prevent corrosion.
In accordance with the objects of this invention, a new method of fabricating an integrated circuit using copper interconnects is achieved. A substrate layer is provided encompassing all underlying layers, devices, and junctions. Conductive plugs are provided in an isolating dielectric layer. A first intermetal dielectric layer is deposited overlying the conductive plugs and the isolating dielectric layer. The first dielectric layer is etched through to the underlying conductive plugs where the first dielectric layer is not protected by a first photoresist mask and where the etching through forms via trenches. A barrier layer is deposited overlying the first dielectric layer and the exposed conductive plugs. A thin copper seed layer is deposited overlying the barrier layer. A copper layer is deposited by electrochemical deposition where the copper seed layer initiates the copper layer deposition, where the copper layer is deposited overlying the barrier layer, and where the copper layer completely fills the via trenches. The copper layer is annealed. An optional dielectric barrier layer is deposited overlying the copper layer. The dielectric barrier layer is etched through to the underlying copper layer where the dielectric barrier layer is not protected by a second photoresist mask and thereby forms a hard mask for the copper layer etch. The copper layer and the barrier layer are etched through to the underlying first dielectric layer where the copper layer is not protected by the dielectric barrier layer hard mask, where the etching through forms conductive traces, and where the dielectric barrier layer hard mask, the copper layer, and the barrier layer are left overlying all of the via trenches. A passivation layer composed of a copper-germanium alloy is formed in the exposed surfaces of the copper layer to complete the conductive traces. A second intermetal dielectric layer is deposited overlying the conductive traces and the first dielectric layer to complete the fabrication of the integrated circuit device.